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LAWRENCE DIFRANCESCO Electronic Engineer (R&D) – Manufacturing & Product Engineer
Colorado Springs, CO 80908, tel: 719-244-2249 fax: 719-495-6555, Email:
[email protected] References on LinkedIn: http://www.linkedin.com/profile/view?id=60109901&locale=en_US&trk=tab_pro Keywords: Flip-chip, CSP, MEMS, MCM, multichip module, wafer level packaging, WLCSP, KGD, Known Good Die, COB, chip on board, fiber optic IC packaging, active fiber optic alignment packaging, wire bonding, Ball bonding, wedge bonding, SMT assembly, fine line copper laminate, fine line thick film, micro via laser drilling
SUMMARY of EXPERIENCE
Over 20+ years experience as a Research Scientist (R&D) with a broad range of “Hands-On” technical expertise, progressive advancements, and increasing responsibility in technology, management leadership roles, raising funds and establishing 2 start-up companies. Raised/managed $2.8M venture capital funds for advance tele-communications micro-relay (MEMS & 11 person company). Raised/managed $1.5M venture capital funds for high-volume PCB production site, 31 person company, 1 mil/min copper plating rate.
Project Leader for “Star Wars” SDI Super Computer, 49 flip-chip MCM using KGD chips 7 layer Polyimide/Copper Transmission Line for Wafer Level High-Density Interconnect (HDI) in production for the F-22 Raptor Digital Signal Processor (DSP) Technical Leader responsible for developing the Flip-chip Wafer Level Chip Scale Packaging (WLCSP) Process (in production at Flip Chip Technology, AZ and Delco, IN)
Won Hughes Aircraft Corporate Superior Performance Award. Because of excellent interpersonal skills, lead production staff to reduce the defect rate from 300,000 defects/ppm to 25 defects/ppm in 6 months at 2 high volume SMT assembly plants, 24 hour/7 day, 350 person. Won Sheldahl Superior Performance Award for Vision and Leadership.
“Hands-On”-Technically competent, business savvy, & customer sensitive in one package. These areas include:
Fiber Optic IC Packaging (10 GB/s Sonet bus at 1310 nm Laser & Pin diode receiver) Advanced Micro-Electronics (49 die MCM using KGD chips, flying on F-22 Raptor) MCM, MEMS, Chip Scale Packaging (CSP), Flip-chip assembly, Smart Cards, RFID Cards Developed +100 GHz connector technology for Production/Test/Burn-In Socket Developed production worthy process for +100 GHz Test/Burn-In/Production Connector Developed +100GHz Chip Scale Packaging (CSP) Test/Burn-In/Production Socket Developed Advanced SMT Assembly techniques – flip chip, BGA, QFN, fine-pitch Used Wire Bonding – Ball, & Wedge – Copper & Gold wire Developed ultra-high performance PCB material with Dk of 2.9 & Df of 0.0009 Developed Environmentally-sealed CSP IC-passivation (withstood MIL-STD 883C) Design of both analog and digital IC’s with extensive experience in digital interface design and high-speed data bus networks (both copper and fiber optics) Developed ultra-low-cost Micro-Via Drilling Process (2 mil dia.) using existing PCB equipment for SMT Developed ultra-fine-grain, high-speed-electroplating process for copper & nickel (1 mil/min) Developed 4x faster Electro-Winnowing Process using 80% less power for refining mining metals Developed 2 mil Line/Space, high-volume PCB process using existing PCB equipment Used CAM software, SurfCAM, to operate CNC vertical mill and CNC turning center (lathe) to create custom sockets, hardware and test equipment sockets Developed Flip-chip Wafer Level Chip Scale Packaging (WLCSP) Process for 0.1 mm Solder Ball pitch Developed CSP Process for CCD sensor in High Radiation Environment Sensor (+300 kRad (SI)) Developed active-self-aligning V-Groove Fiber Optic Data Bus Package for 10 GB/s Sonet 1310 nm Laser & PIN diode GaAs PHEMT receiver Developed ultra-high performance flex printed circuit board (PCB) material with Dk of 2.9 and Df of 0.0009 Raised/managed $2.8M of venture capital funds for advanced tele-communications micro-relay. Raised/managed $1.5M of venture capital funds for high-volume PCB production site Software experience ORCAD, Protel, Solid Works, SurfCAM, CAM350, AutoCAD, SPICE, other CAD/CAM programs.
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Lawrence DiFrancesco
Lawrence DiFrancesco, Colorado Springs, CO 80908 tel: 719-244-2249, fax: 719-495-6555
[email protected] www.PITek.us References on LinkedIn: http://www.linkedin.com/profile/view?id=60109901&locale=en_US&trk=tab_pro Keywords: Flip-chip, CSP, MEMS, MCM, multichip module, wafer level packaging, WLCSP, KGD, Know Good Die, COB, chip on board, fiber optic IC packaging, active fiber optic alignment packaging, wire bonding, Ball bonding, wedge bonding, SMT assembly, fine line copper laminate, fine line thick film, micro via laser drilling
“Hands-On”-Technically competent, business savvy, & customer sensitive in one package.
Explain your experience and type of equipment: +20 years experience as Research Scientist with “Hands-On” laboratory and technical expertise Operated a wide range of equipment and processes including: o electroplating chemistry – copper, nickel, gold metal baths upto 1 mil/min, >400 ASF o photolithography - dryfilm photoresist, liquid photoresist – spin coat, immersion coat, spray coat o high-vacuum processes - evaporator, sputter sphere, ion mill, plasma deposition o molding equipment - small cavity injection mold, pour casting, UV cure materials o coating equipment - roll laminator-coater, vacuum coater, spin-on coater, roll-to-roll coater o pressing equipment – laminator press, vacuum laminator press o bonding process - wire bonding - ball & wedge, flip chip assembly, fine pitch soldering, BGA, QFN, SMT, flux-less soldering, diffusion bonding – room temp & cryogenic temp o furnace equipment – controlled atmosphere hot-plate, controlled atmosphere belt furnace o machining equipment – Micro-Via Laser Drilling – CNC vertical mill , CNC lathe, o fine-line thick film substrate, fine-line thin film – ceramic & organic substrate (1 mil line/space) Developed 4x faster Electro-Winnowing Process using 80% less power for refining mining metals Developed Optical Process Tool for fine-pitch, high volume production line (2 mil Line/Space) Developed Environmentally Sealed IC Process for CSP devices which exceeds MIL-STD 833C Developed 179°C Eutectic Tin/Lead/Silver Solder material and process Explain your fiber optics experience: Developed Active-self-aligning V-Groove Fiber Optic Data Bus Package – 10 GB/s Sonet 1310 nm Laser & PIN Diode GaAs PHMET receiver package / module Design of analog & digital IC’s for Fiber Optic Data Bus and copper data bus Developed Stacked Optical Focal Plane Array – cryogenic temp Developed Fiber Optic Pulling Equipment for Metal Coating Fiber Optic fiber pulling tower Developed Optical Accelerometer MEMS for Delco Airbag Crash Sensor Developed Fiber Optic Towed-Array Sonar Under-Sea cable module Explain your “Testing” experience: Developed +100 GHz Chip Scale Packaging Test/Burn-in/Production Socket System Developed production process for +100 GHz Connector System Developed Test Socket & Process for test & burn-in of CSP devices for Known Good Die (KGD) in MCM Developed “Star Wars” SDI Supercomputer 49 flip-chip MCM using KGD chips for F-22 Fighter DSP Developed test fixtures for MIL-STD 833C testing on CSP devices for KGD chips Developed High-Radiation Environment CCD Sensor Test Socket Developed Ultra-High Performance Printed Circuit Board Flex material for Test Equipment Interconnect Explain your “Functional Testing” experience: Used +100 GHz Chip Scale Packaging Test/Burn-In/Production Socket for testing/speed-grading KGD devices for population of 49 flip-chip MCM “Star Wars” SDI Supercomputer now flying on F-22 Raptor Performed ALL MIL-STD 833C test sequence on CSP devices for KGD chips, +10,000 chips Design/Fabricated/Assembled/Installed +100 GHz for Production Floor Automatic Testing Equipment (ATE) on several vendors supplied equipment Operated Production Floor ATE equipment to confirm +1.5 million insertion lifetime of +100 GHz socket Explain your “Acceptance Testing” experience: Used “Active Acceptance Testing” to map defects and reduced 300,000 defects/ppm to 25 defects/ppm in 6 months at 24 hour/ 7 day high-volume 350-person SMT assembly plant Guided the plant to ISO 9001 and 9002 certification
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AWARDS and ACCOMPLISHMENTS Published 14 papers on Advanced Micro-Electronics/SMT packaging, PCB layout and SMT assembly technologies. Hold 4 patents (2 for ultra-high performance heat exchangers, 1 for Phase Array Radar Antenna), 1 MEMS telecom micro-relay, 3 patents pending. Main Contributor to the SDI “Star Wars” Super Computer project (flying on F-22 Raptor) Project Leader of the Hughes/Delco Automotive Underhood Flip-chip Technology IC process development. Corporate Superior Performance Award recipient, Hughes Aircraft Co. Superior Performance Award for Vision and Leadership, Sheldahl, Inc. Lecturer/Recruiter of Senior Level Engineering Courses at University of California, Irvine. Honorable Mention for Most Valuable Invention Award. Project displayed at GOMAC. 2 projects published in Hughes Aircraft advertisements. At Hughes Aircraft Company, won R&D Grants 10 consecutive years $500,000 per year. These projects included: Project Leader “Star Wars” SDI Super Computer, 49 flip-chip MCM using KGD chips 7 layer Polyimide/Copper Transmission Line for Wafer Level High-Density Interconnect (HDI) in production for the F-22 Raptor Digital Signal Processor (DSP) Technical Leader responsible for developing the Flip-chip Wafer Level Chip Scale Packaging (WLCSP) Process (used at Flip Chip Technology, Phoenix, AZ and Delco) Developed RAD-hard, active-self-aligning V-Groove Fiber Optic Package Project member of Stacked Optical Focal Plane Array for HgCdTe, SiIn, SiGa, SiAs materials Developed Optical Accelerometer MEMS for Delco Airbag Crash Sensor Transmission Line/Integrated Passive Devices on GaAs MEMS for Cannon Launch electronics Developed Electroplating Process to fabricate Air Transmission Lines for Cannon Launch Technical evaluation of Packaging Technology value at MCC Research Consortium, Austin, TX Requested by management to teach and recruit Senior Level Electronic Design class at UC of Irvine, Cal. Corporate Superior Performance Award, Honorable Mention for Most Valuable Invention Award. PROFESSIONAL EXPERIENCE
Rocky Connections, LLC & Creative Engineering Solutions, Colorado Springs, CO, May 97 to Pres
Founder/Research Scientist of privately funded R&D contracted company. Raised/managed $2.8M of venture capital funds for advanced tele-communications micro-relay (MEMS), 11 person. Developed +100 GHz interconnect system for high-volume manufacturing company using advanced high-speed electroplating process (1 mil/min). Developed Environmentally Sealed CSP Chip and Test/Burn-In/Production Socket. Developed 1-mil/minute deposition rate electroplating chemistry, nickel and copper metals Developed ultra-fine-grain, high-speed-electroplating process for electroformed nickel stencils Developed high-performance squeegee blade technology using electroformed nickel metal. Developed and manufactured private labeled Test/Burn-In/Production Sockets and Connectors with +100 GHz bandwidth. Developed and manufactured active self-aligning V-Groove Fiber Optic Laser package for 10 GBps Sonnet 1310 nm Laser/PIN diode package/module. 3 of 7
Other notable customers include: Atmel, Consultant - Developed Flip-chip packaging process, performed failure analysis process. Maxim Integrated Products, Sr. Packaging Scientist Develop specifications, provided leadership, and experience about converting products into CSP format and Flip-Chip format. Developed Failure Analysis (FA) methodology analysis which did not induce False Failures. Mission Research Corporation, Colorado Springs, CO. Scientist/Engineer (SECRET Clearance) Project Leader of newly patented Neutron Particle Detector using CSP packaging of HgCdTe CCD detector with 12 bit A/D resolution at 10 MSamples/sec. Transformed conceptual drawings to practical/manufacturable PCB, developed mechanical drawings, using CSP packaging, SMT assemblies, and contract manufacturing services. Particle Interconnect Corporation, Colorado Springs, CO, June 96 to May 97 Chief Operating Officer, Founder Raised/managed $1.5M venture capital, responsible for the creation, technical leadership, and business management of a highly-automated, high-volume Printed Circuit Board production line (31 people) utilizing a unique production process for a patented technology. Successfully setup high-volume production line process at revolutionary electroplating speed (1 mil/min, >400ASF) for private investor group within initial 3 months of operations. Use of COTS equipment to instrument PCB production lines. Sheldahl Inc., Aberdeen, SD, March 95 to May 96 Senior Technical Specialist Technical Program Manager with overall responsibilities for 2 high-volume, flex-circuit SMT PCB, contract assembly sites (24 hour/7 day, 350 people) using mixed assembly technologies. Worked in both; R&D of assembly processes, screening and training of production personnel during introduction of new manufacturing/assembly processes, and customer interface concerns for production quality control. Developed automation of high-volume production equipment, provided direction in the use and integration of COTS, digital interface design and troubleshooting. Used PC’s, PLC’s and FPGA’s for programmable controllers of production equipment. Raised productivity and lowered reject rates from 300,000 defects/million to 25 defects/million by implementing DOE, DFM and SPC on multiple SMT production lines. Provided technical leadership for implementation of ISO 9001 & 9002 certification. Particle Interconnect Partnership, Minneapolis, MN, December 91 to March 95 Senior Scientist Developed new concepts using an advanced packaging technology for electronic packages, sockets, and connectors in fine-pitch SMT products, BGA, QFP, flip-chip assembly. Responsible for business development, proposal generation, project leadership, and evaluation. Program Manager/SMT Process Engineer Responsible for new products from concept to delivery for broad spectrum (chip level through board level) of new, fine-pitch SMT products, Flip chip, BGA 0.5 mm, QFN 0.2 mm Worked in both R&D and manufacturing to develop and implement high-speed electroplating processes and production equipment.
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Product Manufacturing Manager Responsible for multi-faceted projects of multi-discipline jig and fixture product development for high-volume automatic test equipment products, to include electrical, mechanical, thermal aspects of testing a wide range of semiconductor products and package types. Controlled automatic test equipment (ATE) using PC’s, and programmable devices. Automatic test equipment programmed and tested large quantities of programmable devices including EPROM’s, EEPROM’s, FPGA’s and other programmable devices. Consultant, Silicon Valley, CA, March 91 to December 91 Principle Engineer, and Project Manager. Responsible for Analog Product line development using broad spectrum of SMT processes with interface to SMT contract assembly companies. Hughes Aircraft, Fullerton, CA, January 82 to March 91 Senior Member of Technical Staff / Research Scientist (SECRET and Above Clearance) Project Leader of multi-year Chip-Scale (CSP) and Flip-Chip Packaging development. Project’s main goal was to develop necessary tools to support software, hardware, computer modeling parameters, and test equipment to demonstrate producibility of Chip-Scale (CSP), Flip-Chip, Fine-Line Thick film, Fine-Line Thin film, and MCM technologies, flying on F-22 Raptor. Project developed Environmentally Sealed Chip Scaled Process to meet MIL-STD 883C Project included development of new IC processes, design of both analog and digital IC’s with extensive experience in digital interface design and high-speed data bus networks: fiber optic, twin-ax, and tri-ax data bus, extensive computer modeling of IC and circuit designs. Reported directly to Corporate R&D Director. Performed technical appraisal of MCC technology development for GMAC/Hughes/Delco, $4M/annual membership fee. Century Data Systems, Advanced Systems Program, Anaheim, CA, Sr. Analog Engineer Servo systems, read/write signal path, switching power supplies. March 81 to January 82
Hughes Aircraft, Irvine, CA, June 79 to February 81 Analog Engineer High speed data bus (fiber optic and copper), analog circuit modeler, and designer. Anaconda Telecom, Microelectronics R&D Lab, Anaheim, CA, June 76 to June 79 R&D Engineer Analog circuit design of telephone circuitry and switching power supplies. Developed Solid-State-Relay technology process and components. College interviewer/recruiter team member EDUCATION AAET, Chabot Jr. College, Hayward, CA 1972 BSEE, Cal Poly, San Luis Obispo, CA 1976 18 of 24 credits in Material Science Masters of Science Post Graduate degree program
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1989 CORPORATE SUPERIOR PERFORMANCE AWARD Hughes Aircraft Company
NAME: Lawrence DiFrancesco JOB TITLE: MTS ORGANIZATION: Surveillance & Sensor Systems Division -1F-52-33 Mr. Lawrence DiFrancesco is an MTS in the Radar Processing Department. He is recognized for his expertise in High Density Multi-chip Interconnect (HDMI), VHSIC Packaging Designs and High Density, High Performance Issues. During 1989 he contributed significantly to the following successes. • • Multi-Chip Module (MCM) design, fabrication which is now ready for assembly in a 2" x 4" module. This module is functionally equivalent to several 6" x 9" VSP circuit cards. Designed, fabricated and tested the Analog test substrate circuit that demonstrates the electrical performance of the MCM design and generated the mask sets for the IC face down attachments. Supported development of the process and performed testing that provides environmental protection for face down die. On the Low Cost Phase Shifter, he designed and generated masks required for compatibility with the Delco solder bumping process. The CHIPS were successfully bumped at Delco. Evaluated techniques and performed study on application of the Particle Interconnect (PI) technology to enable die testing at speed and over temperature. Designed and successfully developed for EDSG a TAB Test Socket that enabled testing of incoming TAB mounted parts on their BSTS program. This greatly improved the overall card test yield Developed and demonstrated a revolutionary air bag crash sensor for General Motors (GM). Results are being evaluated by GM.
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In addition to work accomplishments, Mr. DiFrancesco is the GSG representative on the Corporate Micro Electronics Packaging Committee. In 1989 he presented papers at three (3) IEEE Advanced Packaging and Testing Symposiums and was awarded two (2) patent disclosures on the Micro Heat Exchanger.
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High Speed Mining/Metal Plating
Technology has two major advantages over conventional Solvent Extraction/Electro-Winning: Plating rates of a minimum of 10x industry standard [>>200 A/ft 2 vs. 20 A/ft2 industry standard] Save 80% wattage for same current setting [0.6V x 2A = 1.2W vs. 3.6V x 2A = 7.2W industry standard] Kennecott Utah Copper (http://www.kennecott.com/ ) 2.224B Pounds/year @ 0.20KWH/pound @ $0.05/KWH (http://costs.infomine.com/costdatacenter/electricpower.aspx ) for an annual saving
of $17M/year in electricity cost.
These features occur because of an increase in anode/cathode coupling coefficient to the pregnant copper, nickel, etc. solution. This is sometimes attributed to “better wetting”, “better anode design”. The picture shows 2 tests that were run under the exactly same condition of: 44oF solution temperature (higher temperatures give better results) Hull Cell @ 5A for 20 minutes using 4 grams copper/liter in 2% H2SO4 [industry standard is typically 40 grams/liter] This technique is also applicable to the Printed Circuit Board industry with similar results such as: Faster deposition rate (200 ASF vs 20 ASF), Finer copper grain structure, better via fill.
The darker color of lighting conditions). fine grain growth. growth; i.e. higher Connections, LLC)
the upper sample is representative of poor crystal growth (not poor The lighter color of the lower sample is representative of exceptionally There are additional benefits associated with exceptional fine grain strength, higher ductility, higher conductivity, etc. (courtesy Rocky
Existing tanks at the reader’s facility can be re-fitted with the High Speed Plating technology. 7 of 7